An integrated circuit memory device, such as a dynamic random access memory (DRAM) device 11, may include a plurality of data input/output pins 30-1 to 30-n coupled to respective input/output buffers 32-1 to 32-n, as shown in FIG. 1. Moreover, each of the input/output buffers 32-1 to 32-n may include a respective input circuit 10-1 to 10-n and a respective output circuit 20-1 to 20-n. The input/output buffers can thus be used when writing data DQ-1 to DQ-n from the data pins 30-1 to 30-n to memory cell array 40 during a write operation and when reading data DQ-1 to DQ-n from memory cell array 40 during a read operation.
The memory device 11 may also include a mode set decoder 36 that may generate a single mode set signal MSS used to set a characteristic of the output circuits 20-1 to 20-n. More particularly, command signals /CS, /RAS, /CAS, and /WE received by command decoder 35 may specify a read operation, a write operation, or a mode set operation. During read/write operations, signals ADDR received over an address bus at address buffer 37 may define memory cells of array 40 from/to which data is to be read/written. During mode set operations, signals ADDR received over the address bus at mode set decoder 36 may define mode set codes. In response to a mode set code received during a mode set operation, the same mode set signal MSS may be provided to all of the output circuits 20-1 to 20-n so that all of the output circuits 20-1 to 20-n are set to a same mode of operation. A single mode set signal MSS, however, may be unable to provide separate control of individual output circuits.
The integrated circuit memory device 12 of FIG. 2 may include input/output buffers 32-1 to 32-n coupled between respective data input/output pins 30-1 to 30-n and memory cell array 40, as discussed above with respect to FIG. 1. Moreover, each of the data input/output buffers 32-1 to 32-n may include a respective input circuit 10-1 to 10-n and a respective output circuit 20-1 to 20-n. In addition, the memory device 12 includes a command decoder 35, an address buffer 36, and mode set controller 38. The mode set controller 38 includes mode set decoders 38-1 to 38-n corresponding to each of the input/output buffers 32-1 to 32-n so that a separate mode set signal MSS1 to MSSn is generated for each respective input/output buffer 32-1 to 32-n. Accordingly, separate control of a same characteristic of the input/output buffers may be provided. The plurality of separate lines between the mode set controller 38 and each of the input/output buffers 32-1 to 32-n, however, may be undesirable.
Independent output driver calibration is also discussed for example in U.S. Patent Publication No. 2002/0049556, the disclosure of which is hereby incorporated herein in its entirety by reference. As discussed in U.S. Patent Publication No. 2002/0049556, characteristics of multiple drivers for output buffer circuits may be independently adjusted or calibrated without significantly increasing the associated necessary circuitry. A central control logic circuit initiates the calibration process of the drivers. A serial communication link is provided between the control logic and each of the output drivers. The serial link reduces the number of lines that are required to communicate between the central control logic and the multiple output drivers. The output drivers can be calibrated one at a time, and a handoff is made from one driver to the next to start the calibration of the subsequent driver.